In a semiconductor device manufacturing method using a silicon wafer (hereinafter, referred to as “wafer”), a film forming process of forming a conductive film and an insulating film on a surface of a wafer, a lithography process of forming a photoresist layer of a predetermined pattern on the conductive film and the insulating film, an etching process of forming a wiring groove or a contact hole in the insulating film or forming a conductive film as a gate electrode by a plasma generated from a processing gas by using the photoresist layer as a mask, and the like are repeatedly performed.
For example, in a certain electronic device manufacturing method, a groove is formed in a predetermined pattern in a polysilicon film formed on a surface of a wafer and, then, a SiO2 layer is formed to fill the groove. Next, the SiO2 layer is removed by etching or the like until a predetermined thickness thereof is obtained.
As a method for removing the SiO2 layer, there is known a substrate processing method for performing a COR (Chemical Oxide Removal) process and a PHT (Post Heat Treatment) process on the wafer. In the COR process, a by-product is generated by chemical reaction between the SiO2 layer and gas molecules. In the PHT process, the by-product generated on the wafer by the chemical reaction of the COR process is removed from the wafer by evaporation or sublimation by heating the wafer that has been subjected to the COR process.
As a substrate processing apparatus for performing the substrate processing method including the COR process and the PHT process, there is known a substrate processing apparatus including a chemical reaction processing chamber (COR processing chamber) and a heat treatment chamber (PHT processing chamber) connected to the chemical reaction processing chamber (see, Japanese Patent Application Publication No. 2008-160000). In addition, there is known a substrate processing apparatus for performing, in the same processing chamber, a COR process on a wafer at a low temperature and then a PHT process at a temperature increased to a predetermined level by heating the wafer (see Japanese Patent Application Publication No. 2007-266455).
However, in the substrate processing apparatus in which the chemical reaction processing chamber and the heat treatment chamber are separately provided, the number of the processing chambers is increased and, also, a transfer unit for transferring the wafer between the chemical reaction processing chamber and the heat treatment chamber is required. Due to the installation space of the transfer unit, the entire substrate processing apparatus is scaled up. Further, a wafer transfer time is increased, so that a productivity is decreased. Meanwhile, even in the substrate processing apparatus for performing the chemical process and the heat treatment in the same processing chamber, time for changing the temperature of the wafer is required, so that it is difficult to improve the productivity.